The present invention relates to the plasma etching of a silicon wafer. More particularly, the present invention relates to methods for etching through a Borophosphosilicate Glass (BPSG) layer of a silicon wafer layer stack in the manufacture of an integrated circuit (IC).
In semiconductor IC fabrication, devices such as component transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. Successive layers of various materials may be deposited onto the wafer or substrate to form a layer stack. With reference to a silicon wafer layer stack 100 illustrated in FIG. 1A, for example, a TiSi.sub.2 layer 102 may be formed above a silicon wafer 104. The TiSi.sub.2 layer may have many functions, including functioning as an interconnecting layer. When used as an interconnecting layer, the TiSi.sub.2 layer may be patterned and etched in a conventional manner to form interconnect lines for coupling various devices of the IC together to form the desired circuit. A BPSG layer 106 may be formed over the TiSi.sub.2 layer to act as a dielectric layer.
It should be noted that the layer stack of FIG. 1A is shown for illustration purposes only and other additional layers, which have not been described, may be present above and below the TiSi.sub.2 layer and the BPSG layer. These other layers may be used to provide, for example, additional interconnecting layers or layers from which components may be formed.
In order to electrically interconnect portions of the aforementioned TiSi.sub.2 layer to other layers and/or devices, contacts may be formed which extend through the BPSG dielectric layer. These contacts may be formed by etching contact openings through the BPSG layer using a suitable photoresist technique to pattern and mask the BPSG layer. The photoresist layer represents a layer of conventional photoresist material, which is capable of being patterned for etching, e.g., through exposure to ultra-violet rays. This patterning process removes portions of the photoresist layer and exposes certain portions of the BPSG layer for etching.
To illustrate, FIG. 1A shows portions of an overlaying photoresist (PR) layer that remain after the patterning step, including portions 108a and 108b atop BPSG layer 106. An opening through the photoresist mask is indicated by open region 110 in FIG. 1A. Through the photoresist mask, the BPSG layer may then be etched to form the contact openings. To actually make the electrical contact, the contact opening through BPSG layer 106 may be filled in a conventional manner with an appropriate electrically conductive material such as aluminum, titanium, various aluminum and titanium alloys, and the like.
Each of the described layers of layer stack 100 is readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes. These processes may include, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
In the design of a BPSG etch process, e.g., to provide the aforementioned contact openings through the BPSG layer, many considerations must be taken into account. Among these considerations is etch rate selectivity, i.e., how well an etch process discriminates between the target BPSG layer and other layers from which material removal is undesired. To provide a reliable and commercially advantageous etching process, etching regimes which exhibit a high etch rate selectivity between the different layers of the layer stack are desirable. Manufacturers measure the etch rate selectivity, or simply selectivity, by the ratio of the etch rate of a particular etch process through a particular layer compared to the etch rate of that etch process through another layer of the layer stack. In the case of etching through a BPSG layer down to a TiSi.sub.2 layer, a high BPSG to TiSi.sub.2 selectivity is usually desired.
Another consideration in the design of an etch process relates to etch rate uniformity, i.e., how uniform an etch process is at different regions of the wafer. If the etch rate uniformity is poor, for example, the etch rate in the central region of the wafer may be much faster than the etch rate in the peripheral regions of the wafer. One common approach measures the depth of the etch at various locations on the wafer, e.g., 17 in one case, and calculates a percentage variation based on these measurements by, for example, taking the maximum etch rate minus the minimum etch rate and dividing by two times the average etch rate.
Another consideration relates to etch rate loading. Etch rate loading has recently gained more attention since modern IC circuits are scaled with increasingly narrower design rules to achieve greater circuit density. As a result, the feature sizes such as the width of the interconnect lines and the width of contacts formed to interconnect the features have steadily decreased. As the feature sizes shrink, it becomes increasingly difficult to achieve a uniform etch rate both in the region where the features are closely spaced, i.e., the narrow spacings, and in the region where there are open fields, i.e., the wider spacings.
For some etch processes, the etch rate in the narrow spacings may be slower than that in the wider spacings or open field regions. This phenomenon, referred herein as the loading in etch rates, may be a consequence of microloading and aspect ratio-dependent etching (ARDE). Microloading or RIE lag refers primarily to the situation wherein the etch rate is reduced in smaller contacts or trenches when compared to larger contacts or trenches in the same location on the wafer. It can also be said that the aspect ratio of large or small contacts or trenches are different and therefore the etch exhibits ARDE. The loading in etch rates causes trenches to be formed in the layer stack at different rates. This etch rate loading tends to become more severe when opening widths fall below about 0.8 microns, and especially when opening widths fall below about 0.5 microns. As a result of the etch rate variations, by the time the desired etching is complete in areas having a slow etch rate (e.g., in the narrower openings), overetching (e.g., the inadvertent removal of materials from underlying layers) may have already occurred in areas having a higher etch rate (e.g., the open field regions or larger openings).
Another consideration relates to the profile angle of the etch. Profile angles has become a more significant issue as the feature sizes on the wafer shrink. Profile angle refers to the angle the sidewalls of an etch opening forms with the horizontal plane of the wafer. Generally an anisotropic or vertical sidewall (i.e., a profile angle of 90 degrees) is desired. However, different process chemistries and parameters may result in, for example, the undercutting of the sidewalls (i.e., profile angles greater than 90 degrees) or sloped sidewalls (i.e., profile angles less than 90 degrees). It is believed that the sloped sidewalls or low profile angles may be caused by an excessive polymer buildup along the sidewalls during the etching process, which prevents the proper vertical etching of the sidewall.
For illustration purposes, the phenomenon of etch rate loading and profile angle will be described with reference to FIG. 1B, which illustrates the same layer stack shown in FIG. 1A after the completion of a hypothetical BPSG etch process. Etch rate loading, as mentioned, refers to the difference in the rate of etching in regions of the wafer having dense features (i.e., narrow openings) compared to open field regions. To determine the etch rate loading for a particular etching regime, a partial etch may be performed. Referring to FIG. 1B, dashed lines 114 and 116 indicate the depth to which the layer stack is etched by the partial etch. Due to the etch rate loading phenomenon, the depth D.sub.2 of the etch within narrow openings, illustrated by opening 118, is not as deep as depth D.sub.1 in more open regions, illustrated by open region 120. Etch rate loading may be quantified by the equation (D.sub.1 -D.sub.2)/D.sub.1 .times.100! to express the etch rate loading as a percentage of the etch depth. With respect to profile angles, line 122 in FIG. 1B represents a sidewall formed in opening 118 which exhibits a profile angle of less than the desired 90 degree vertical sidewall (indicated by the dashed lines in FIG. 1B)
In the prior art, there exist many BPSG etch processes. However, these processes were typically optimized for a particular set of requirements, e.g., high BPSG to polysilicon or for different geometries. As technology changes, however, IC chip manufacturers continually search for ways to improve BPSG etch results. In view of the foregoing, what is desired are improved methods and apparatus for etching a BPSG layer, particularly for etching down through the BPSG layer to a TiSi.sub.2 layer in a wafer layer stack.